Layout versus schematic in multilayered printed electronics designs

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TypeArticle
ConferenceLOPEC 2017, 28-30 March, 2017, Munich, Germany
Abstract
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LanguageEnglish
AffiliationNational Research Council Canada; Information and Communication Technologies
Peer reviewedNo
NPARC number23002550
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Record identifierc5134719-c0de-404f-9738-220b8c6360bd
Record created2017-11-29
Record modified2017-11-29
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